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Integrated Circuit Systems, Inc.
ICS952607 Advance Information
Programmable Timing Control HubTM for Next Gen P4TM processor
Recommended Application: CK409 Compliant clock for Next Gen P4 Processor Output Features: * 2 - 0.7V current-mode differential CPU pairs * 1 - 0.7V current-mode differential SRC pair * 9 - PCI, 3 free running, 33MHz * 3 - REF, 14.318MHz * 3 - 3V66, 66.66MHz * 1 - VCH/3V66, selectable 48MHz or 66MHz * 2 - 48MHz * 1 - 24/48MHz Key Specifications: * CPU/SRC outputs cycle-cycle jitter < 125ps * 3V66 outputs cycle-cycle jitter < 250ps * PCI outputs cycle-cycle jitter < 250ps * +/- 300ppm frequency accuracy on CPU & SRC clocks Features/Benefits: * QuadRomTM frequency selection. * Programmable output frequency. * Programmable asynchronous 3V66&PCI frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz reference input. * Supports tight ppm accuracy clocks for Serial-ATA * Supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread * Supports CPU clks up to 400MHz
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0 CPU FS4 FS3 FS2 FS1 FS0 MHz 100.00 0 0 0 0 0 200.00 0 0 0 0 1 133.33 0 0 0 1 0 166.67 0 0 0 1 1 0 0 1 0 0 200.00 0 0 1 0 1 400.00 0 0 1 1 0 266.67 0 0 1 1 1 333.33 100.99 0 1 0 0 0 201.98 0 1 0 0 1 134.65 0 1 0 1 0 168.31 0 1 0 1 1 1 115.00 0 1 0 0 230.00 0 1 1 0 1 153.33 0 1 1 1 0 191.67 0 1 1 1 1 1 100.00 0 0 0 0 200.00 1 0 0 0 1 133.33 1 0 0 1 0 166.67 1 0 0 1 1 0 1 0 0 200.00 1 400.00 1 0 1 0 1 266.67 1 0 1 1 0 333.33 1 0 1 1 1 105.00 1 1 0 0 0 210.00 1 1 0 0 1 140.00 1 1 0 1 0 175.00 1 1 0 1 1 1 110.00 1 1 0 0 220.00 1 1 1 0 1 146.66 1 1 1 1 0 1 1 1 1 1 183.34
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Pin Configuration
AGP MHz 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 67.33 67.33 67.33 67.32 76.66 76.66 76.66 76.66 66.66 66.66 66.66 71.43 66.66 66.66 66.66 66.66 69.99 69.99 69.99 69.99 73.33 73.33 73.33 73.33 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.66 33.66 33.66 33.66 38.33 38.33 38.33 38.33 33.33 33.33 33.33 35.71 33.33 33.33 33.33 33.33 35.00 35.00 35.00 35.00 36.66 36.66 36.66 36.66
*FS1/REF0 1 48 VDDA *FS0/REF1 2 47 GND REF2 3 46 IREF VDDREF 4 45 Reset# X1 5 44 GND X2 6 43 CPUCLKT1 GND 7 42 CPUCLKC1 **FS2/PCICLK_F0 8 41 VDDCPU **FS4/PCICLK_F1 9 40 CPUCLKT0 PCICLK_F2 10 39 CPUCLKC0 38 GND VDDPCI 11 37 SRCCLKT GND 12 36 SRCCLKC ^^PCICLK0 13 35 VDD PCICLK1 14 34 VttPWR_GD/PD# PCICLK2 15 33 SDATA PCICLK3 16 32 SCLK VDDPCI 17 31 3V66_0 GND 18 30 3V66_1 PCICLK4 19 29 GND PCICLK5 20 **Sel24_48#/24_48MHz 21 28 VDD3V66 27 3V66_2 **FS3/48MHz_0 22 26 3V66_3/VCH 48MHz_1 23 25 VDD48 GND 24 * This pin have 120K pull-up to VDD ** This pin have 120K pull-down to GND ^^ An external 2.2K pull-down resistor is needed on this pin ICS952607
48-pin SSOP
Note: FS1 and FS0 are equal to Intel CK409-defined FSA and FSB, respectively.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
Integrated Circuit Systems, Inc.
ICS952607 Advance Information
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PIN NAME *FS1/REF0 *FS0/REF1 REF2 VDDREF X1 X2 GND **FS2/PCICLK_F0 **FS4/PCICLK_F1 PCICLK_F2 VDDPCI GND ^^PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 **Sel24_48#/24_48MHz **FS3/48MHz_0 48MHz_1 GND VDD48 3V66_3/VCH 3V66_2 VDD3V66 GND 3V66_1 3V66_0 SCLK SDATA VttPWR_GD/PD# VDD SRCCLKC SRCCLKT GND CPUCLKC0 CPUCLKT0 VDDCPU CPUCLKC1 CPUCLKT1 GND Reset# IREF GND VDDA PIN TYPE I/O I/O OUT PWR IN OUT PWR I/O I/O OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT I/O I/O OUT PWR PWR OUT OUT PWR PWR OUT OUT IN I/O IN PWR OUT OUT PWR OUT OUT PWR OUT OUT PWR OUT OUT PWR PWR DESCRIPTION Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. 14.318 MHz reference clock. Ref, XTAL power supply, nominal 3.3V Crystal input,nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Frequency select latch input pin / 3.3V PCI free running clock output. Frequency select latch input pin / 3.3V PCI free running clock output. Free running PCI clock not affected by PCI_STOP# . Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24mHz, 0 = 48MHz. Frequency select latch input pin / Fixed 48MHz clock output. 3.3V 48MHz clock output. Ground pin. Power for 24 & 48MHz output buffers and fixed PLL core. 3.3V 66.66MHz clock output / 48MHz VCH clock output. 3.3V 66.66MHz clock output Power pin for the 3V66 clocks. Ground pin. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Clock pin of I2C circuitry 5V tolerant Data pin for I2C circuitry 5V tolerant This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the device into a low power state. Power supply, nominal 3.3V Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Ground pin. "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. Ground pin. 3.3V power for the PLL core.
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Integrated Circuit Systems, Inc.
ICS952607 Advance Information
General Description
ICS952607 is a 48 pin clock chip following Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS952607 is driven with a 14.318MHz crystal. It generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA suuport. The ICS952607 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment. This part also provides 128 frequency selections via ICS QuadROMTM technology as an alternate to M/N programming.
Block Diagram
Frequency Dividers
PLL2
48MHz (1:0) 24_48MHz
X1 X2
XTAL
REF (2:0)
CPUCLKT (1:0) SCLK SDATA VTTPWRGD# PD# FS (4:0) Sel24_48# Control Logic Programmable Spread PLL1 Programmable Frequency Dividers CPUCLKC (1:0) STOP Logic SRCCLKT SRCCLKC 3V66 (3:0) PCICLK (5:0) PCICLK_F (2:0) RESET# I REF
Power Groups
Pin Number VDD GND 4 7 28 29 11,17 12,18 35 38 41 44 48 47 25 24 Description Xtal, Ref 3V66 PCICLK outputs SRCCLK outputs CPU outputs MCLK, CPU Analog, CPU digital 48MHz Fix, Fix Digital, Fix analog
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Integrated Circuit Systems, Inc.
ICS952607 Advance Information
Table1: QuadRom Frequency Selection Table
Bit6 Bit5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit4 Bit3 Bit2 Bit1 Bit0 FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.00 200.00 133.33 166.67 200.00 400.00 266.67 333.33 100.99 201.98 134.65 168.31 115.00 230.00 153.33 191.67 100.00 200.00 133.33 166.67 200.00 400.00 266.67 333.33 105.00 210.00 140.00 175.00 110.00 220.00 146.66 183.34 AGP MHz 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 67.33 67.33 67.33 67.32 76.66 76.66 76.66 76.66 66.66 66.66 66.66 71.43 66.66 66.66 66.66 66.66 69.99 69.99 69.99 69.99 73.33 73.33 73.33 73.33 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.66 33.66 33.66 33.66 38.33 38.33 38.33 38.33 33.33 33.33 33.33 35.71 33.33 33.33 33.33 33.33 35.00 35.00 35.00 35.00 36.66 36.66 36.66 36.66 Spread % 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0.35% Center 0.35% Center 0.35% Center 0.35% Center No Spread No Spread No Spread No Spread 0.35% Center 0.35% Center 0.35% Center 0.35% Center 0.35% Center 0.35% Center 0.35% Center 0.35% Center No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread
Table continued on next page.
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Integrated Circuit Systems, Inc.
ICS952607 Advance Information
Table1: QuadRom Frequency Selection Table (Continued)
Bit6 Bit5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit4 Bit3 Bit2 Bit1 Bit0 CPU AGP MHz 68.66 68.66 68.66 68.66 68.66 68.66 68.66 68.66 69.99 69.99 69.99 69.99 69.99 69.99 69.99 69.99 71.33 71.33 71.33 71.33 71.33 71.33 71.33 71.33 73.33 73.33 73.33 73.33 73.33 73.33 73.33 73.33 PCI MHz 34.33 34.33 34.33 34.33 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 35.00 35.00 35.00 35.00 35.66 35.66 35.66 35.66 35.66 35.66 35.66 35.66 36.66 36.66 36.66 36.66 36.66 36.66 36.66 36.66 Spread % No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread
FS4 FS3 FS2 FS1 FS0 MHz 0 0 0 0 0 103.00 0 0 0 0 1 206.00 0 0 0 1 0 137.33 0 0 0 1 1 171.67 0 0 1 0 0 228.89 0 0 1 0 1 412.00 0 0 1 1 0 274.67 0 0 1 1 1 343.33 0 1 0 0 0 105.00 0 1 0 0 1 210.00 0 1 0 1 0 140.00 0 1 0 1 1 175.00 0 1 1 0 0 233.33 0 1 1 0 1 420.00 0 1 1 1 0 280.00 0 1 1 1 1 350.00 1 0 0 0 0 107.00 1 0 0 0 1 214.00 1 0 0 1 0 142.66 1 0 0 1 1 178.34 1 0 1 0 0 237.78 1 0 1 0 1 428.00 1 0 1 1 0 285.34 1 0 1 1 1 356.66 1 1 0 0 0 110.00 1 1 0 0 1 220.00 1 1 0 1 0 146.66 1 1 0 1 1 183.34 1 1 1 0 0 244.44 1 1 1 0 1 440.00 1 1 1 1 0 293.34 1 1 1 1 1 366.66
Table continued on next page.
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Integrated Circuit Systems, Inc.
ICS952607 Advance Information
Table1: QuadRom Frequency Selection Table 3 (Continued)
Bit6 Bit5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit4 Bit3 Bit2 Bit1 Bit0 CPU AGP MHz 63.33 63.33 63.33 63.33 63.33 63.33 63.33 63.33 59.99 59.99 59.99 59.99 59.99 59.99 59.99 59.99 56.66 56.66 56.66 56.66 56.66 56.66 56.66 56.66 53.33 53.33 53.33 53.33 53.33 53.33 53.33 53.33 PCI MHz 31.66 31.66 31.66 31.66 31.66 31.66 31.66 31.66 30.00 30.00 30.00 30.00 30.00 30.00 30.00 30.00 28.33 28.33 28.33 28.33 28.33 28.33 28.33 28.33 26.66 26.66 26.66 26.66 26.66 26.66 26.66 26.66 Spread % No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread
FS4 FS3 FS2 FS1 FS0 MHz 0 0 0 0 0 95.00 0 0 0 0 1 190.00 0 0 0 1 0 126.66 0 0 0 1 1 158.34 0 0 1 0 0 211.11 0 0 1 0 1 380.00 0 0 1 1 0 253.34 0 0 1 1 1 316.66 0 1 0 0 0 90.00 0 1 0 0 1 180.00 0 1 0 1 0 120.00 0 1 0 1 1 150.00 0 1 1 0 0 200.00 0 1 1 0 1 360.00 0 1 1 1 0 240.00 0 1 1 1 1 300.00 1 0 0 0 0 85.00 1 0 0 0 1 170.00 1 0 0 1 0 113.33 1 0 0 1 1 141.67 1 0 1 0 0 188.89 1 0 1 0 1 340.00 1 0 1 1 0 226.67 1 0 1 1 1 283.33 1 1 0 0 0 80.00 1 1 0 0 1 160.00 1 1 0 1 0 106.66 1 1 0 1 1 133.34 1 1 1 0 0 177.78 1 1 1 0 1 320.00 1 1 1 1 0 213.34 1 1 1 1 1 266.66
Table continued on next page.
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Integrated Circuit Systems, Inc.
ICS952607 Advance Information
Table1: QuadRom Frequency Selection Table 4 (Continued)
Bit6 Bit5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit4 Bit3 Bit2 Bit1 Bit0 CPU AGP MHz 76.66 76.66 76.66 76.66 76.66 76.66 76.66 76.66 79.99 79.99 79.99 79.99 79.99 79.99 79.99 79.99 51.99 51.99 51.99 51.99 51.99 51.99 51.99 51.99 50.00 50.00 50.00 50.00 50.00 50.00 50.00 50.00 PCI MHz 38.33 38.33 38.33 38.33 38.33 38.33 38.33 38.33 40.00 40.00 40.00 40.00 40.00 40.00 40.00 40.00 26.00 26.00 26.00 26.00 26.00 26.00 26.00 26.00 25.00 25.00 25.00 25.00 25.00 25.00 25.00 25.00 Spread % No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread
FS4 FS3 FS2 FS1 FS0 MHz 0 0 0 0 0 115.00 0 0 0 0 1 230.00 0 0 0 1 0 153.33 0 0 0 1 1 191.67 0 0 1 0 0 255.55 0 0 1 0 1 460.00 0 0 1 1 0 306.67 0 0 1 1 1 383.33 0 1 0 0 0 115.00 0 1 0 0 1 230.00 0 1 0 1 0 153.33 0 1 0 1 1 191.67 0 1 1 0 0 255.55 0 1 1 0 1 460.00 0 1 1 1 0 306.67 0 1 1 1 1 383.33 1 0 0 0 0 78.00 1 0 0 0 1 156.00 1 0 0 1 0 104.00 1 0 0 1 1 130.00 1 0 1 0 0 173.33 1 0 1 0 1 312.00 1 0 1 1 0 208.00 1 0 1 1 1 260.00 1 1 0 0 0 75.00 1 1 0 0 1 150.00 1 1 0 1 0 100.00 1 1 0 1 1 125.00 1 1 1 0 0 166.67 1 1 1 0 1 300.00 1 1 1 1 0 200.00 1 1 1 1 1 250.00
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ICS952607 Advance Information
I C Table: Frequency Select Register
Byte 0 Bit 7 Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name FS Source FS6 FS5 FS4 FS3 FS2 FSA FSB
6 5 4 3 2 1 0
Control Function Frequency H/W IIC Select Freq Select Bit 6 Freq Select Bit 5 Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0
Type RW RW RW RW RW RW RW RW
0 Latch Inputs
1 IIC
PWD 0 0 0 0 0 0 0 0
See Table 1: QuadRom Frequency Selection Table
I C Table: Spreading and Device Behavior Control Register
Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin # 37,36 43,42 40,39
Name SS1 SS0 SS_EN WDS_EN SRC/SRC# Reserved CPUCLKT/C_1 CPUCLKT/C_0
Control Function Spread Select 1 Spread Select 0 Spread Enable Control WD Soft Reset Enable Output Control Reserved Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 00 = 0.35% 01 = 0.50% ON ON Disable Disable Disable
1 10 = 0.75% 11 = No Spread OFF OFF Enable Enable Enable
PWD 0 0 1 0 1 1 1 1
I C Table: Output Control Register
Byte 2 Bit 7 Bit 6 Bit 5 Bit Bit Bit Bit Bit 4 3 2 1 0 27 Pin # Name SRC Stop Mode Reserved CPUT Stop Mode Reserved 3V66_2 Reserved Reserved Reserved Control Function 0: SRCT Driven during PD#; 1: Tri-stated Reserved 0: CPUT Driven during PD#; 1: Tri-stated Reserved Output Control Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 Driven Driven Disable 1 Hi-Z Hi-Z Enable PWD 0 0 0 0 1 1 1 1
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I C Table: Output Control Register
Byte 3 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # 20 19 16 15 14 13
Name ASEL1 Reserved PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
7 6 5 4 3 2 1 0
Control Function 3V66/PCI Freq Select Reserved Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0
1
PWD 0 0 1 1 1 1 1 1
See Table 5: Async AGP/PCI Freq Table Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable
I C Table: Output Control Register
Byte 4 Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit
2
Pin #
Name 48MHz_0 2x output drive SRCFS
Control Function 0=2x drive SRC Frequency Select Reserved Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW
0 2x drive 100MHz Disable Disable Disable Disable Disable
1 normal 200MHz Enable Enable Enable Enable Enable
PWD 0 0 0 1 1 1 1 1
5 4 3 2 1 0
30 31 10 9 8
Reserved 3V66_1 3V66_0 PCICLK_F2 PCICLK_F1 PCICLK_F0
I C Table: Reserved Register
Byte 5 Bit 7 Bit Bit Bit Bit Bit Bit Bit 6 5 4 3 2 1 0 26 Pin # Name 3V66_3/VCH Select Mode Sel1 Mode Sel0 3V66_3/VCH M PLL2 Div3 M PLL2 Div2 M PLL2 Div1 M PLL2 Div0 Control Function Output Select PLL Mode Selection Bits Output Control M Divider Programming bits for Async mode 2&3 Type RW RW RW RW RW RW RW RW 0 3V66 1 VCH PWD 0 0 0 1 X X X X
See Table 4: Mode Selection Table Disable Enable
The decimal representation of M PLL2 Div (3:0) + 2 is equal to REF divider value for PLL2
Table 3: Linear M/N AGP/PCI Programmable Frequency Example
Hex B5b3:0 Hex B6b6:0 AGP Freq C B A 7 6 D C B A D
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PCI Freq 32.58 32.62 32.67 32.89 33.01 33.07 33.15 33.24 33.34 33.61
Hex B5b3:0 Hex B6b6:0 AGP Freq C 7 B A C B A C 9 6 33 1E 2F 2B 34 30 2C 35 28 1B 67.44 67.57 67.70 68.01 68.58 68.93 69.34 69.73 69.83 70.01
PCI Freq 33.72 33.78 33.85 34.01 34.29 34.47 34.67 34.86 34.91 35.01
31 2D 29 1D 19 36 32 2E 2A 37
65.15 65.24 65.34 65.79 66.01 66.14 66.30 66.47 66.68 67.21
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ICS952607 Advance Information
Table 4: Mode Selection Table
Mode IIC Control CPU M/N Overclocking SRC M/N Overclocking AGP/PCI M/N Overclocking Spreading Standard Overclock Mode Byte 5 bit(6:5) = 00 Byte 11 & 12 Byte 11 & 12 Byte 11 & 12 All clocks have spread. All clocks oveclock together by Byte 11&12 M/N programming. Simple async AGP/PCI overclocking w/o using M/N programming. CPU Overclock Mode Byte 5 bit(6:5) = 01 Byte 11 & 12 Byte 5 & 6 (asynchronous) Byte 5 & 6 (asynchronous) Only CPU clocks have spread. CPU overclock by Byte 11&12 SRC/AGP/PCI overclock by Byte 5&6 asynchronously. SRC can be kept at 100 w/o spread yet AGP/PCI can be overclocked. Graphic Overclock Mode Byte 5 bit(6:5) = 10 Byte 11 & 12 Byte 11 & 12 Byte 5 & 6 (asynchronous) Latch input shoud be set as FS(4:0) = 10xxx. CPU & SRC have spread. CPU/SRC overclock by Byte 11&12 AGP/PCI overclock by Byte 5&6 asynchronously. Simple async AGP/PCI overclocking w/o using M/N programming.
Remark Mode B (B6&B3 bit 7) AGP/PCI can be selected to be overclock from 66/33, 72/36 or 80/40.
Table 5: Asynchronous 3V66/PCI Frequency Table
Byte6 Bit7 0 0 1 Byte3 Bit7 0 1 0 3V66/PCI Frequency 66.66/33.33 80.00/40.00 72.73/36.36
I C Table: Vendor & Revision ID Register
Byte 6 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name ASEL0 N PLL2 Div6 N PLL2 Div5 N PLL2 Div4 N PLL2 Div3 N PLL2 Div2 N PLL2 Div1 N PLL2 Div0
7 6 5 4 3 2 1 0
Control Function 3V66/PCI Freq Select
Type RW RW RW RW RW RW RW RW
0
1
PWD 0 X X X X X X X
See Table 4: Async AGP/PCI Freq Table
N Divider Programming bits for Async mode 2&3
The decimal representation of N PLL2 Div (6:0) + 8 is equal to VCO divider value for PLL2.
I C Table: Vendor & Revision ID Register
Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function REVISION ID Type R R R R R R R R 0 1 PWD X X X X 0 0 0 1
VENDOR ID
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I C Table: Byte Count Register
Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
Control Function
Type RW RW RW RW RW RW RW RW
0
1
PWD 0 0 0 0 1 1 1 1
7 6 5 4 3 2 1 0
Byte Count Programming b(7:0)
Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes.
I C Table: Watchdog Timer Register
Byte 9 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
7 6 5 4 3 2 1 0
Control Function WD Timer Bit 7 WD Timer Bit 6 WD Timer Bit 5 WD Timer Bit 4 WD Timer Bit 3 WD Timer Bit 2 WD Timer Bit 1 WD Timer Bit 0
Type RW RW RW RW RW RW RW RW
0
1
PWD 0 0 0 0 1 0 1 1
These bits represent X*290ms the watchdog timer waits before it goes to alarm mode. Default is 11 x 293ms = 3.2s.
I C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10 Bit 7 Bit 6 Bit 5 Bit Bit Bit Bit Bit
2
Pin # -
Name M/NEN WDEN WDFSEN WD SF4 WD SF3 WD SF2 WD SF1 WD SF0
Control Function M/N Programming Enable Watchdog Enable WD Safe Frequency Mode Watch Dog Safe Freq Programming bits
Type RW R RW RW RW RW RW RW
0 Disable Disable Latched FS/Byte0
1 Enable Enable WD B10 b(4:0)
PWD 0 1 0 0 0 0 0 0
4 3 2 1 0
Writing to these bit will configure the safe frequency as Byte0 bit (4:0).
I C Table: VCO Frequency Control Register
Byte 11 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name N Div8 M Div6 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Prog bit 8 Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
M Divider Programming bits
The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(8:0)+8] / [MDiv(6:0)+2]
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I C Table: VCO Frequency Control Register
Byte 12 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0
Control Function
Type RW RW RW RW RW RW RW RW
0
1
PWD X X X X X X X X
7 6 5 4 3 2 1 0
N Divider Programming b(8:0)
The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(8:0)+8] / [MDiv(6:0)+2]
I C Table: Spread Spectrum Control Register
Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Control Function
Type RW RW RW RW RW RW RW RW
0
1
PWD X X X X X X X X
7 6 5 4 3 2 1 0
Spread Spectrum Programming b(7:0)
These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming.
I C Table: Spread Spectrum Control Register
Byte 14 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name Reserved Reserved SSP13 SSP12 SSP11 SSP10 SSP9 SSP8
7 6 5 4 3 2 1 0
Control Function Reserved Reserved
Type R R RW RW RW RW RW RW
0 -
1 -
PWD 0 0 X X X X X X
Spread Spectrum Programming b(13:8)
These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming.
I C Table: Output Divider Control Register
Byte 15 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name SRC Div3 SRC Div2 SRC Div1 SRC Div0 CPU Div3 CPU Div2 CPU Div1 CPU Div0 Control Function SRC Divider Ratio Programmaing Bits Type RW RW RW RW RW RW RW RW 0000:/2 0001:/3 0010:/5 0011:/7 0000:/2 0001:/3 0010:/5 0011:/7 0 0100:/4 0101:/6 0110:/10 0111:/14 0100:/4 0101:/6 0110:/10 0111:/14 1000:/8 1001:/12 1010:/20 1011:/28 1000:/8 1001:/12 1010:/20 1011:/28 1 1100:/16 1101:/24 1110:/40 1111:/56 1100:/16 1101:/24 1110:/40 1111:/56 PWD X X X X X X X X
CPUDivider Ratio Programmaing Bits
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I C Table: Output Divider Control Register
Byte 16 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name Reserved Reserved Reserved Reserved 3V66Div3 3V66Div2 3V66Div1 3V66Div0
7 6 5 4 3 2 1 0
Control Function Reserved Reserved Reserved Reserved 3V66 Divider Ratio Programmaing Bits
Type RW RW RW RW RW RW RW RW
0 0000:/2 0001:/3 0010:/5 0011:/7
1 0100:/4 1000:/8 1100:/16 0101:/6 1001:/12 1101:/24 0110:/10 1010:/20 1110:/40 0111:/14 1011:/28 1111:/56
PWD X X X X X X X X
I C Table: Output Divider Control Register
Byte 17 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name Reserved 3V66INV SRCINV CPUINV Reserved Reserved Reserved Reserved
7 6 5 4 3 2 1 0
Control Function Reserved 3V66 Phase Invert SRC Phase Invert CPU Phase Invert Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 Default Default Default -
1 Inverse Inverse Inverse -
PWD X X X X 0 0 0 0
I C Table: Group Skew Control Register
Byte 18 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
7 6 5 4 3 2 1 0
Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 0 0 0 0 0 0 0 0
I C Table: Group Skew Control Register
Byte 19 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name 3V66Skw3 3V66Skw2 3V66Skw1 3V66Skw0 PCISkw3 PCISkw2 PCISkw1 PCISkw0 Control Function CPU-3V66 7 Step Skew Control (ps) Type RW RW RW RW RW RW RW RW 0 0000:0 0001:N/A 0010:N/A 0011:N/A 0000:0 0001:N/A 0010:N/A 0011:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A 1 1000:300 1001:N/A 1010:N/A 1011:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A 1100:450 1101:600 1110:750 1111:900 1100:450 1101:600 1110:750 1111:900 PWD 0 0 0 0 1 1 0 0
CPU-PCI 7 Step Skew Control (ps)
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I C Table: Group Skew Control Register
Byte 20 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name PCISkw3 PCISkw2 PCISkw1 PCISkw0 Reserved Reserved Reserved Reserved
Control Function CPU-PCI F(2:0) 7 Step Skew Control (ps) Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 0000:0 0001:N/A 0010:N/A 0011:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A
1 1000:300 1001:N/A 1010:N/A 1011:N/A 1100:450 1101:600 1110:750 1111:900
PWD 1 1 0 0 0 0 0 0
7 6 5 4 3 2 1 0
I C Table: Slew Rate Control Register
Byte 21 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name PCIFStr1 PCIFStr0 Reserved Reserved Reserved Reserved AGPStr1 AGPStr0
7 6 5 4 3 2 1 0
Control Function PCICLKF (2:0) Strength Control Reserved Reserved Reserved Reserved AGPCLK Strength Control
Type RW RW RW RW RW RW RW
0 00 = 0.63X 01 = 0.75X 00 = 0.70X 01 = 0.80X
1 10 = 0.88X 11 = 1.00X 10 = 0.90X 11 = 1.00X
PWD 1 1 1 1 1 1 1 1
I C Table: Slew Rate Control Register
Byte 22 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name REF_Slw PCIFStr1 PCIFStr0 PCIFStr1 PCIFStr0 PCIFStr1 PCIFStr0
Control Function REF Slew Rate Control PCICLK (5) Strength Control PCICLK (4:2) Strength Control PCICLK (1:0) Strength Control
Type RW RW RW RW RW
0 00 = Medium 01 = Weak 00 = 0.63X 01 = 0.75X 00 = 0.63X 01 = 0.75X 00 = 0.63X 01 = 0.75X
1 10 = Strong 11 = N/A 10 = 0.88X 11 = 1.00X 10 = 0.88X 11 = 1.00X 10 = 0.88X 11 = 1.00X
PWD 1 0 1 1 1 1 1 1
7 6 5 4 3 2 1 0
I C Table: Output Control Register
Byte 23 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 22 21 2 1 3 23 Pin # Name 48MHz_0 24_48MHz REF1 REF0 REF2 48MHz_1 Reserved Reserved Control Function Output Control Output Control Output Control Output Control Output Control Output Control Reserved Reserved Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 0 0
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I C Table: Read Back Register
Byte 24 Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit 5 4 3 2 1 0 Pin # Name WDHRB WDSRB Reserved FS4RB FS3RB FS2RB FSARB FSBRB Control Function WD Hard Alarm Status Read back WD Soft Alarm Status Read back Reserved FS4 Read back FS3 Read back FS2 Read back FSA Read back FSB Read back Type R R R R R R R R 0 1 PWD X X 0 X X X X X
2
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Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND -0.5 V to VDD + 0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input MID Voltage Input Low Voltage Input High Current SYMBOL VIH VMID VIL IIH I IL1 Input Low Current I IL2 Operating Supply Current Powerdown Current Input Frequency 3 Pin Inductance1 Input Capacitance
1
CONDITIONS 3.3V +/-5% 3.3V +/-5% 3.3V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock. Triangular Modulation
MIN 2 1 VSS 0.3 -5 -5 -200
TYP
MAX VDD + 0.3 1.8 0.8 5
UNITS NOTES V V V uA uA uA
IDD3.3OP I DD3.3PD Fi Lpin CIN COUT CINX4
350 35 12 14.31818 7 5 6 5 1.8 30 33
mA mA mA MHz nH pF pF pF ms kHz
3 1 1 1 1 1,2 1
Clk Stabilization1,2 Modulation Frequency
1 2
TSTAB
Guaranteed by design, not 100% tested in production. See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 4 Crystal recommendations: CL = 20pF and Shunt cap. Max = 5pF.
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Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3V +/-5%; CL =2pF PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew Jitter, Cycle to cycle
1 2
SYMBOL Zo1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm tr tf d-t r d-t f dt3 t sk3 t jcyc-cyc
CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V
MIN 3000 660 -150 -300 250
TYP
MAX
UNITS
NOTES 1 1
850 mV 150 1150 550 140 mV mV mV ppm ps ps ps ps % ps ps
1 1 1 1 1 1,2 1 1 1 1 1 1 1
-300 175 175
300 700 700 125 125 55 100 125
Measurement from differential wavefrom VT = 50% Measurement from differential wavefrom
45
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
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Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values IOH = -1 mA Output High Voltage VOH I OL = 1 mA Output Low Voltage VOL V OH@MIN = 1.0 V Output High Current I OH VOH@MAX = 3.135 V VOL @MIN = 1.95 V Output Low Current I OL V OL@MAX = 0.4 V Rising edge rate Edge Rate Edge Rate Falling edge rate V OL = 0.4 V, VOH = 2.4 V Rise Time t r1 V OH = 2.4 V, VOL = 0.4 V Fall Time t f1 Duty Cycle Skew Jitter
1
MIN -300 2.4 -33
TYP
MAX 300 0.55 -33
30 1 1 0.5 0.5 45 38 4 4 2 2 55 250 250
UNITS ppm V V mA mA mA mA V/ns V/ns ns ns % ps ps
Notes 1,2
1 1 1 1 1 1 1
dt1 t sk1 t jcyc-cyc
V T = 1.5 V V T = 1.5 V VT = 1.5 V 3V66
Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Long Accuracy Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew Jitter
1 2
SYMBOL ppm VOH VOL IOH IOL
CONDITIONS see Tperiod min-max values I OH = -1 mA I OL = 1 mA V OH@MIN = 1.0 V VOH@MAX = 3.135 V V OL@MIN = 1.95 V V OL@MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V V T = 1.5 V 3V66
MIN -300 2.4 -33
TYP
MAX 300 0.55 -33
UNITS ppm V V mA mA mA mA V/ns V/ns ns ns % ps ps
Notes 1,2
30 38 1 1 0.5 0.5 45 4 4 2 2 55 500 250
t r1 t f1 dt1 tsk1 t jcyc-cyc
1 1 1 1 1 1 1
Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
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Electrical Characteristics - VCH, 48MHz, 24MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Long Accuracy Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew Long Term Jitter
1
SYMBOL ppm VOH VOL I OH I OL
CONDITIONS see Tperiod min-max values I OH = -1 mA I OL = 1 mA V OH@MIN = 1.0 V VOH@MAX = 3.135 V VOL @MIN = 1.95 V VOL@MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V 125us period jitter (8kHz frequency modulation amplitude)
MIN -200 2.4 -33
TYP
MAX 200 0.55 -33
UNITS Notes ppm V V mA mA mA mA V/ns V/ns ns ns % ns ns 1,2
30 1 1 1 1 45 38 2 2 2 2 55 1 6
1 1 1 1 1 1 1
t r1 t f1 dt1 t sk1
Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
2
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70C; V DD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Long Accuracy Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew Duty Cycle Jitter
1
SYMBOL ppm VOH1 VOL1 IOH1 IOL1 tr11 tf11 tsk11 dt11 tjcyc-cyc 1 V
CONDITIONS see Tperiod min-max values IOH = -1 mA I OL = 1 mA
OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, V OH = 2.4 V
MIN -300 2.4
TYP
MAX 300 0.4
UNITS ppm V V mA mA ns ns ps % ps
Notes 1
-29 29 1 1 45
-23 27 2 2 500 55 1000
1 1 1 1 1
VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Guaranteed by design, not 100% tested in production.
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ICS952607 Advance Information
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
VARIATIONS N 48
10-0034
D mm. MIN 15.75 MAX 16.00 MIN .620
D (inch) MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
Ordering Information
ICS952607yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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